Design-Reuse2h
MosChip Technologies joins Renesas RZ Partner Ecosystem as AI/ML Design Partner
MosChip® Technologies is now an AI/ML design partner under Renesas RZ partner ecosystems, delivering intelligent solutions ...
Design-Reuse3h
RISC-V Announces Ratification of the RVA23 Profile Standard
Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads ...
Design-Reuse3h
Logic Fruit Technologies Welcomes Mr. Gurudutt (GD) Bansal as Senior Vice President Engineering
Logic Fruit Technologies is pleased to announce the appointment of Mr. Gurudutt (GD) Bansal as the Senior Vice President ...
Design-Reuse19h
Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension
Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier ...
Design-Reuse21h
Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance
Open access to complete SDK with Linux kernel will simplify building and testing of CHERI-enabled RISC-V applications ...
Design-Reuse21h
Arteris and SiFive Deliver Pre-verified Solution for the Datacenter Market
The collaboration enables SoC designers to reduce project risk and integrate Arteris Ncore cache coherent interconnect IP and ...
Design-Reuse21h
Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance ...